Pat Gelsinger joined Intel at 18 as a technician after skipping his last 1.5 years of high school. He became engineer number 4 on the 386 and architect and design manager of the 486, earning bachelor’s, master’s and PhD degrees along the way. He later served as Intel’s CTO, VMware’s CEO and Intel’s CEO, and is now a general partner at Playground Global. The tension he describes: AI is making chip design easy, which pushes the bottleneck into manufacturing, memory, packaging and power. The conversation moves from the 486 and AI-driven design to the AI chip shakeout, memory and stacking, optics, energy and agents. These signals are from an interview that Raghu Raghuram and Guido Appenzeller did with Pat Gelsinger on the a16z podcast.
The Design
Inventing the Toolchain. The 486 was the first chip built with modern electronic design automation (EDA) methods, Gelsinger says, because the tools did not yet exist. With no Verilog, the team wrote an Intel hardware description language and built its compiler. With no automatic place-and-route, Intel worked with Alberto Sangiovanni-Vincentelli and his Berkeley students on the first automated placement, routing and timing. The chip’s lasting legacy, he argues, was the foundation it laid for today’s EDA industry. ↗ 6:05
AI’s 486 Moment. Chip design is entering a transition like the 486’s, Gelsinger says, when asked whether Nvidia’s Blackwell will be remembered as the last chip designed before AI took over. Many logic functions can now be done with AI tools, he explains, because transistor budgets are large and the tools are smarter. Analog blocks such as SerDes remain hard because they need lots of silicon data. His working model for the new era: a few experts guiding the tools. ↗ 7:25
Design in 3, Wait 9. Faster design alone does not speed up a chip, Gelsinger argues. Even if AI tools yield a strong design in 3 months, fab takes at least 3 more, advanced 3D packaging another 3 and rack-scale integration the rest, because “nothing’s a chip anymore. It’s a rack.” Masks can cost $50 million before a prototype exists. He wants that 9-month tail cut to 1 or 2 months, since 18 months to scale leaves workload assumptions out of date. ↗ 9:46
Memory and Power Walls. Memory is the next bottleneck, and Gelsinger calls high-bandwidth memory (HBM) “a hideous memory,” though the best available. Its bit density is poor, its bandwidth is capped by the chip’s edge, or shoreline, and DRAM dislikes the heat beside compute. Power is the other wall. Weak 3D power-modeling tools force designers to reserve safety margin across almost the full envelope, losing about 40% of power. Better power modeling, he says, is the fix. ↗ 11:56
The Shakeout
100 Chips Won’t Last. Today’s roughly 100 AI inference chips will converge to a few, Gelsinger predicts, for 3 reasons. Splitting fleets into prefill, decode and midfill tiers is not sustainable, and some now want CPU-like hardware again for reasoning models. Models themselves will shift toward 3D, chemistry and 64-bit precision work. And scale takes capital and workloads, so players such as OpenAI, Nvidia and Anthropic will pick winners by how hardware and software co-evolve. ↗ 14:50
Big Players Absorb Variety. A host pushes back: if AI agents can write optimized kernels overnight, the software cost that once limited the industry to 1 or 2 architectures disappears. Gelsinger agrees the bottleneck moves, but to manufacturing and capital, since deploying a new chip at scale can mean $50 billion in data centers and power commitments. Big players will absorb the variety instead, as Nvidia did with Groq. In 2 years, he predicts, nobody will spot Groq inside Nvidia. ↗ 19:14
The Stack
30 Years, Zero New Memories. No major new memory has emerged in 30 years, Gelsinger says, despite close to 100 attempts he knows of and at least 5 he worked on, Optane among them. The industry still runs on DRAM, SRAM and flash, partly because memory made money only 1 year in 5, starving R&D. AI has flipped that: a host notes all 3 big memory makers now rank among the 20 most valuable companies. Gelsinger, backing a stealth memory startup, expects that capital to fund real innovation. ↗ 22:46
3 to 5 High. Asked how tall chips will get, Gelsinger bets on modest stacks. Each added layer raises the value at risk, so per-layer yield must improve exponentially, which makes 16- or 32-high stacks impractical. He expects 3 to 5 layers, with 2- or 4-high memory, to be the sweet spot. Add vertical power delivery and redistribution layers, and a package is already about 8 layers thick before optics. His verdict: an engineering feat and a manufacturing nightmare. ↗ 27:19
Keep Memory Close. Gelsinger rejects 2 alternatives to stacking. Moving memory off-package over optical links burns power, because moving a bit costs about 1,000 times more energy than a compute operation. Processing-in-memory (PIM) forces workloads into small pieces pushed into memory, which he finds too constraining. PIM ideas have circulated for 25 to 30 years, he notes, and will likely still be circulating 25 to 30 years from now. His preference: dense, high-bandwidth memory placed close to compute. ↗ 32:14
Copper’s Long Goodbye. All I/O should move to optics, Gelsinger argues, though not the core compute-memory complex. He says he declared copper dead about 25 years ago and will eventually be right: copper at 5 meters now costs more than optics at 100 meters. He expects co-packaged or near-packaged optics around 2028 to 2029. Nvidia’s NVL72, which he calls an engineering marvel and a manufacturing nightmare, took the industry an extra 18 months to digest because optical supply chains were immature. ↗ 34:54
Flows, Not Packets. AI networks should be built for predictable traffic, Gelsinger says. Citing Stanford’s Nick McKeown, he notes that classic networks assume any packet can go anywhere with no advance knowledge, while AI moves large, predictable flows. That points toward optical circuit switching once optics reach the compute complex. A host calls the scale-up versus scale-out split somewhat artificial, and Gelsinger agrees the boundary dissolves once a scale-up domain is big enough. ↗ 38:03
The Power
Energy Is the Ceiling. Energy capacity will cap how far the AI buildout can go, Gelsinger argues. The US spent 10 to 15 years retiring coal about as fast as it added renewables, leaving capacity flat. His line: “energy capacity equals economic capacity.” Growth is now about 4% a year, renewables depend heavily on China, and gas turbine lead times run 8 years. He expects more data center projects to default as buyers ask whether they have the energy to back their GPU commitments. ↗ 43:15
The Revenge of Edison. Power delivery inside data centers has to get far more efficient, Gelsinger says, starting with 800-volt DC, which removes conversion steps kept for historical and standards reasons. His phrase: “the revenge of Edison is upon us.” He points to vertical gallium nitride, where Playground has a company, as a way to step 800 volts down to 48, 12 or even 5 in one conversion. Solid-state transformers and cooling follow, which he calls a renaissance for hardware engineers. ↗ 46:17
CMOS Has Flatlined. Better delivery and cooling are not enough, Gelsinger says; the physics of compute has to change. By his account, CMOS has not improved power per teraflop across the last 5 generations of Nvidia chips, a flatline he calls unacceptable. His example of a different path is Snowcap, Playground’s superconducting company, which he says could deliver 1,000 times better power performance. He expects some of those physics changes in the near future. ↗ 48:02
The Next Layer
VMware for Agents. Every innovation leads to a new abstraction, says Gelsinger, a former VMware CEO, and the virtual machine still deserves a place. Agent swarms need management, security profiles and performance tuning, so each element of virtualization must be rebuilt, down to a vMotion for agents. A host adds that agents are less patient than humans and may pick the VM themselves. Humans still set the policies, Gelsinger says, pointing to Dario’s constitution as one form of guardrail. ↗ 48:47
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